`timescale 1ns / 1ps
module tb_sys_array ();
    parameter DW = 8;

    reg clk=1;
    reg rst;
    reg data_rst;
    reg ini;
    reg data_en;
    reg [DW-1:0] act0;
    reg [DW-1:0] act1;
    reg [DW-1:0] act2;
    reg [DW-1:0] wei0;
    reg [DW-1:0] wei1;
    reg [DW-1:0] wei2;

    wire [DW*2-1:0] 	sum0;
    wire [DW*2-1:0] 	sum1;
    wire [DW*2-1:0] 	sum2;

    always #25 clk = ~clk;
    initial begin
        #1;
        rst = 1;
        data_rst = 1;
        ini = 1;
        data_en = 1;
        #10;
        rst = 0;
        #10;
        rst = 1;
        #30;
        ini = 0;
        wei0 = 1;
        wei1 = 1;
        wei2 = 2;
        #50;
        wei0 = 2;
        wei1 = 2;
        wei2 = 4;
        #50;
        wei0 = 3;
        wei1 = 3;
        wei2 = 6;
        #50;
        ini = 1;
        #50;

        data_en = 0;
        act0 = 1;
        #50;
        act0 = 2;
        act1 = 4;
        #50;
        act0 = 3;
        act1 = 5;
        act2 = 7;
        #50;
        act1 = 6;
        act2 = 8;
        #50;
        act2 = 9;
        #50;
        data_en = 1;
        
    end

    sys_array #(
        .DW 		( DW 		))
    u_sys_array(
        //ports
        .clk      		( clk      		),
        .rst      		( rst      		),
        .data_rst 		( data_rst 		),
        .ini      		( ini      		),
        .data_en  		( data_en  		),
        .act0     		( act0     		),
        .act1     		( act1     		),
        .act2     		( act2     		),
        .wei0     		( wei0     		),
        .wei1     		( wei1     		),
        .wei2     		( wei2     		),
        .sum0     		( sum0     		),
        .sum1     		( sum1     		),
        .sum2     		( sum2     		)
    );

endmodule